class quick_reg_access_seq extends host_if_base_seq;

`uvm_object_utils(quick_reg_access_seq)

function new(string name = "quick_reg_access_seq");
	super.new(name);
endfunction

task body:
	super.body();
	// read from all the registers
	rm.RXD.read(status, data, .parent (this));
	rm.IER.read(status, data, .parent(this)):
	rm.IID.read(status, data, parent(this));
	rm.LCR.read(status, data, parent(this));
	rm.MCR.read(status, data, parent(this));
	rm.LSR.read(status, data, parent(this));
	rm.MSR.read (status, data, parent(this));
	rm.DIV1.read(status, data, .parent(this));
	rm.DIV2.read(status, data, parent(this));

	// write to all the registers
	data = 32'haa;
	rm.TXD.write(status, data, .parent(this));
	rm.IER.write(status, data, .parent(this));
	rm.FCR.write(status, data, .parent(this));
	rm.LCR.write(status, data, .parent(this));
	rm.MCR.write(status, data, .parent(this));
	rm.LSR.write(status, data, .parent(this));
	rm.MSR.Write(status, data, .parent(this));
	rm.DIV1.write(status, data, .parent(this));
	rm.DIV2.write(status, data, .parent(this));

	// read back again
	rm.RXD.read(status, data, .parent(this));
	rm.IER.read(status, data, .parent(this));
	rm.IID.read(status, data, .parent(this));
	rm.LCR.read(status, data, .parent(this));
	rm.MCR.read(status, data, .parent(this));
	rm.LSR.read(status, data, .parent(this));
	rm.MSR.read(status, data, .parent(this));
	rm.DIV1.read(status, data, .parent(this));
	rm.DIV2.read(status, data, .parent(this));

endtask

endclass : quick_reg_access_seq